Avago Technologies LSI53C896 - Manual (Page 168)

4-56 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x19
Chip Test One (CTEST1)
Read Only
FFL Byte Full in DMA FIFO [7:0]
These status bits identify the top bytes in the DMA FIFO
that are full. Each bit corresponds to a byte lane in the
DMA FIFO. For example, if byte lane three is full, then
FFL3 is set. Because the FFL flags indicate the status of
bytes at the top of the FIFO, if all FFL bits are set, the
DMA FIFO is full.
Register: 0x1A
Chip Test Two (CTEST2)
Read Only (bit 3 write)
DDIR Data Transfer Direction 7
This status bit indicates which direction data is being
transferred. When this bit is set, the data is transferred
from the SCSI bus to the host bus. When this bit is clear,
the data is transferred from the host bus to the SCSI bus.
SIGP Signal Process 6
This bit is a copy of the SIGP bit in the
Interrupt Status Zero (ISTAT0) register (bit 5). The SIGP bit
signals a running SCRIPTS instruction. When this register
is read, the SIGP bit in the ISTAT0 register is cleared.
CIO Configured as I/O 5
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space.
7 0
FFL
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
DDIR SIGP CIO CM PCICIE TEOP DREQ DACK
0 0 x x 0 0 0 1