Avago Technologies LSI53C896 - Manual (Page 43)

PCI Functional Description 2-15
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.1.4.5 Examples
The examples in this section employ the following abbreviations:
MR = Memory Read; MRL = Memory Read Line; MRM = Memory Read
Multiple; MW = Memory Write; MWI = Memory Write and Invalidate.
Read Example 1 – Burst = 4 Dwords; Cache Line Size = 4 Dwords:
A to B: MRL (6 bytes)
A to C: MRL (13 bytes)
A to D: MRL (15 bytes)
MR (2 bytes)
C to D: MRM (5 bytes)
C to E: MRM (15 bytes)
MRM (6 bytes)
D to F: MRL (15 bytes)
MRL (16 bytes)
MR (1 byte)
A to H: MRL (15 bytes)
MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MR (2 bytes)
A to G: MRL (15 bytes)
MRL (16 bytes)
MRL (16 bytes)
MRL (16 bytes)
MR (3 bytes)