Avago Technologies LSI53C896 - Manual (Page 252)

5-24 SCSI SCRIPTS Instruction Set
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
ImmD Immediate Data [15:8]
This 8-bit value is used as a second operand in logical
and arithmetic functions.
A7 Upper Register Address Line [A7] 7
This bit accesses registers 0x80–0xFF.
R Reserved [6:0]
5.4.2 Second Dword
Figure 5.8 Read/Write Instruction – Second Dword
DA Destination Address [31:0]
This field contains the 32-bit destination address where
the data is to move.
5.4.3 Read-Modify-Write Cycles
During these cycles the register is read, the selected operation is
performed, and the result is written back to the source register.
The Add operation increments or decrements register values (or memory
values if used in conjunction with a Memory-to-Register Move operation)
for use as loop counters.
Subtraction is not available when SCSI First Byte Received (SFBR) is
used instead of data8 in the instruction syntax. To subtract one value
from another when using SFBR, first XOR the value to subtract
(subtrahend) with 0xFF, and add 1 to the resulting value. This creates the
twos complement of the subtrahend. The two values are then added to
obtain the difference.
5.4.4 Move to/from SFBR Cycles
All operations are read-modify-writes as shown in Table 5.1 . However,
two registers are involved, one of which is always the
SCSI First Byte Received (SFBR) . The possible functions of this
instruction are:
31 0
DSPS Register