Avago Technologies LSI53C896 User Manual
Page 161
SCSI Registers
4-49
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
FF4
FIFO Flags, Bit 4
4
This is the most significant bit in the SCSI FIFO Flags field,
with the rest of the bits in
. For
a complete description of this field, refer to the definition
for
bits [7:4].
SPL1
Latched SCSI parity for SD[15:8]
3
This active HIGH bit reflects the SCSI odd parity signal
corresponding to the data latched into the most significant
byte in the
register.
DIFF
Diffsens Mismatch
2
This bit is set when the DIFFSENS pin detects a SE or
LVD SCSI operating voltage level while the LSI53C896 is
operating in HVD mode (by setting the DIF bit in the
register). If this bit is cleared,
the DIFFSENS value matches the DIF bit setting.
LDSC
Last Disconnect
1
This bit is used in conjunction with the Connected (CON)
bit in
. It allows the user to
detect the case in which a target device disconnects, and
then some SCSI device selects or reselects the
LSI53C896 SCSI function. If the Connected bit is
asserted and the LDSC bit is asserted, a disconnect is
indicated. This bit is set when the Connected bit in
SCNTL1 is off. This bit is cleared when a Block Move
instruction is executed while the Connected bit in
SCNTL1 is on.
SDP1
SCSI SDP1 Parity Signal
0
This bit represents the present state of the SCSI SDP1/
parity signal. It is unlatched and may change as it is read.