Avago Technologies LSI53C896 User Manual
Page 198
4-86
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
To set the GPIO registers, follow these steps:
1.
Read the contents of the GPCNTL register.
2.
Read the contents of the GPREG register.
3.
Write the GPREG register.
4.
Write the GPCNTL register to control the pin for output/input.
ME
Master Enable
7
The internal bus master signal is presented on GPIO1 if
this bit is set, regardless of the state of bit 1 (GPIO1).
FE
Fetch Enable
6
The internal opcode fetch signal is presented on GPIO0
if this bit is set, regardless of the state of bit 0 (GPIO0).
LEDC
LED_CNTL
5
The internal connected signal (bit 3 of the
Interrupt Status Zero (ISTAT0)
register) is presented on
GPIO0 if this bit is set and bit 6 of GPCNTL is cleared and
the chip is not in progress of performing an EEPROM
autodownload regardless of the state of bit 0 (GPIO0).
This provides a hardware solution to driving a SCSI activity
LED in many implementations of LSI Logic SCSI chips.
GPIO
GPIO Enable
[4:2]
General purpose control, corresponding to bit 4 in the
register and the GPIO4 pin.
GPIO4 powers up as a general purpose output, and
GPIO[3:2] power-up as general purpose inputs.
GPIO
GPIO Enable
[1:0]
These bits power-up set, causing the GPIO1 and GPIO0
pins to become inputs. Clearing these bits causes
GPIO[1:0] to become outputs.