Avago Technologies LSI53C896 - Manual (Page 361)

Index IX-11
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
RAM 2-4 , 2-21
running (SRUN) 4-54
SCSI
ATN condition - target mode (M/A) 4-76
bit mode change (SBMC) 4-82
bus control lines (SBCL) 4-41
bus data lines (SBDL) 4-105
bus interface 2-35 , 2-40
bus mode change (SBMC) 4-78
byte count (SBC) 4-115
C_D/ signal (C_D) 4-47
chip ID (SCID) 4-32
clock (SCLK) 3-13 , 4-93
control enable (SCE) 4-95
control one (SCNTL1) 2-28 , 4-24
control three (SCNTL3) 2-41 , 2-42 , 4-30
control two (SCNTL2) 2-52 , 4-27
control zero (SCNTL0) 2-28 , 4-21
cumulative byte count 4-116
data high impedance (ZSD) 4-61
destination ID (SDID) 4-37
disconnect unexpected (SDU) 4-27
encoded destination ID 5-21
FIFO test read (STR) 4-97
FIFO test write (STW) 4-98
first byte received (SFBR) 4-38
function A GPIO signals 3-11
function A signals 3-13
function B GPIO signals 3-12
function B signals 3-16
functional description 2-19
gross error (SGE) 4-77 , 4-80
hysteresis of receivers 6-10
I_O/ signal (I/O) 4-47
input data latch (SIDL) 4-99
input filtering 6-9
instructions
block move 5-5
I/O 5-15
read/write 5-23
interface signals 3-13
interrupt enable one (SIEN1) 2-45 , 4-78
interrupt enable zero (SIEN0) 2-28 , 2-45 , 4-76
interrupt pending (SIP) 4-52
interrupt status one (SIST1) 2-44 , 2-45 , 2-47 , 2-49 , 4-
82
interrupt status zero (SIST0) 2-28 , 2-44 , 2-45 , 2-47 ,
2-49 , 4-79
interrupts 2-48
isolation mode (ISO) 4-93
longitudinal parity (SLPAR) 4-83
loopback mode (SLB) 2-26 , 4-95
low level mode (LOW) 4-96
LVDlink 2-35
mode (SMODE[1:0]) 4-100
MSG/ signal (MSG) 4-47
output control latch (SOCL) 4-39
output data latch (SODL) 2-53 , 2-54 , 2-55 , 4-101
parity control 2-29
parity error (PAR) 4-77
parity errors and interrupts 2-29
performance 1-6
phase 5-13 , 5-29
phase mismatch - initiator mode 4-76
registers 4-19
reset condition (RST) 4-77
RST/ received (RST) 4-81
RST/ signal (RST) 4-45
SCRIPTS operation 5-2
sample instruction 5-3
SDP0/ parity signal (SDP0) 4-45
SDP1/ parity signal (SDP1) 4-49
selected as ID (SSAID) 4-92
selector ID (SSID) 4-40
serial EEPROM access 2-57
status one (SSTAT1) 2-28 , 4-46
status two (SSTAT2) 2-28 , 4-48
status zero (SSTAT0) 2-28 , 4-44
synchronous offset maximum (SOM) 4-93
synchronous offset zero (SOZ) 4-92
synchronous transfer period (TP[2:0]) 4-33
termination 2-38
test four (STEST4) 4-100
test one (STEST1) 4-93
test three (STEST3) 4-97
test two (STEST2) 2-26 , 4-95
test zero (STEST0) 4-92
timer one (STIME1) 4-88
timer zero (STIME0) 4-87
timing diagrams 6-60
TolerANT technology 1-5
transfer (SXFER) 2-42 , 4-33
true end of process 4-58
Ultra2 SCSI 2-23
valid (VAL) 4-40
wide residue (SWIDE) 2-53 , 2-54 , 4-84
SCSI high impedance mode (SZM) 4-95
SCSI-1
transfers
(differential 4.17 Mbytes) 6-63
(single-ended 5.0 Mbytes) 6-63
SCSI-2
fast transfers
10.0 Mbytes (8-bit transfers)
40 MHz Clock 6-64
50 MHz Clock 6-64