Avago Technologies LSI53C896 - Manual (Page 359)

Index IX-9
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
mailbox one (MBOX1) 2-43 , 4-55
mailbox zero (MBOX0) 2-43 , 4-54
manual start mode (MAN) 4-70
MAS0/ 3-19
MAS1/ 3-19
masking 2-46
master
control for set or reset pulses (MASR) 4-63
data parity error (MDPE) 4-42 , 4-71
enable (ME) 4-86
parity error enable (MPEE) 4-62
max SCSI synchronous offset (MO[4:0]) 4-35
Max_Lat (ML) 4-16
maximum stress ratings 6-2
MCE/ 3-19
memory
address strobe 0 3-19
address strobe 1 3-19
address/data bus 3-19
chip enable 3-19
I/O address/DSA offset 5-40
move 2-10
move instructions 2-24 , 5-34
no flush option 2-24
move read selector (MMRS) 4-107
move write selector (MMWS) 4-108
output enable 3-19 , 3-20
read 2-12
read caching 2-12
read command 2-6
read line 2-11 , 2-13
read line command 2-8
read multiple 2-11 , 2-13
read multiple command 2-7
space 2-3 , 2-4
to memory 2-19
to memory moves 2-19
write 2-12 , 2-13
write and invalidate 2-11
write and invalidate command 2-9
write caching 2-13
write command 2-6
write enable 3-19
min_gnt (MG) 4-15
MOE/_TESTOUT 3-19 , 3-20
move to/from SFBR cycles 5-24
multiple cache line transfers 2-9
MWE/ 3-19
N
new capabilities (NC) 4-6
new features in the LSI53C896 1-3
next item pointer register 4-16
Next_Item_Ptr (NIP) 4-16
no download mode 2-58
no flush 5-35
store instruction only 5-39
normal/fast memory ( 128 Kbytes)
multiple byte access read cycle 6-50
multiple byte access write cycle 6-52
single byte access read cycle 6-46
single byte access write cycle 6-48
O
opcode 5-10 , 5-15 , 5-23 , 5-27
fetch burst capability 2-25
operating conditions 6-2
operating register/SCRIPTS RAM read
32-bits 6-18
64-bits 6-19
operating register/SCRIPTS RAM write
32-bits 6-20
64-bits 6-21
operator 5-23
output
current as a function of output voltage 6-11
output signals 6-5 , 6-7
P
PAR 3-6
PAR64 3-7
parallel ROM interface 2-55
parallel ROM support 2-56
parity 2-29 , 3-6
error 3-9
(PAR) 4-81
options 2-27
parity64 3-7
PCI
addressing 2-3
bus commands and encoding types 2-5
bus commands and functions supported 2-4
cache line size register 2-9
cache mode 2-11
command register 2-9
commands 2-4
configuration info enable (PCICIE) 4-57
configuration register read 6-16
configuration register write 6-17
configuration registers 4-1
configuration space 2-3
external memory interface timing diagrams 6-14
functional description 2-3
I/O space 2-4