Avago Technologies LSI53C896 - Manual (Page 60)

2-32 Functional Description
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.2.13 Data Paths
The data path through the LSI53C896 is dependent on whether data is
being moved into or out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.
Figure 2.4 shows how data is moved to/from the SCSI bus in each of the
different modes.
Figure 2.4 LSI53C896 Host Interface SCSI Data Paths
The following items determine whether any bytes remain in the data path
when the chip halts an operation:
2.2.13.1 Asynchronous SCSI Send
Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the
Chip Test Five (CTEST5) register cleared), look at the
DMA FIFO (DFIFO) and DMA Byte Counter (DBC) registers and
calculate whether there are bytes left in the DMA FIFO. To make
this calculation, subtract the seven least significant bits of the
DBC register from the 7-bit value of the DFIFO register. AND
the result with 0x7F for a byte count between zero and 112.
If the DMA FIFO size is set to 944 bytes (bit 5 of the
Chip Test Five (CTEST5) register is set), subtract the 10 least
PCI Interface
DMA FIFO
(8 Bytes x 118)
SODL Register
SCSI Interface
PCI Interface
DMA FIFO
(8 Bytes x 118)
SIDL Register
SCSI Interface
PCI Interface
DMA FIFO
(8 Bytes x 118)
SODL Register
SCSI Interface
SODR Register
PCI Interface
DMA FIFO
(8 Bytes x 118)
SCSI Interface
SCSI FIFO
(1 or 2 Bytes x 31)
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
Synchronous
SCSI Send
Synchronous
SCSI Receive
SWIDE Register SWIDE Register