Avago Technologies LSI53C896 - Manual (Page 292)

6-24 Specifications
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Table 6.24 Burst Opcode Fetch, 32-Bit Address and Data
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid 2 11 ns
t
4
Side signal input setup time 10 – ns
t
5
Side signal input hold time 0 – ns
t
6
CLK to side signal output valid – 12 ns
t
7
CLK HIGH to GPIO0_FETCH/ LOW – 20 ns
t
8
CLK HIGH to GPIO0_FETCH/ HIGH – 20 ns
t
9
CLK HIGH to GPIO1_MASTER/ LOW – 20 ns
t
10
CLK HIGH to GPIO1_MASTER/ HIGH – 20 ns