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Avago Technologies LSI53C896 User Manual

Page 245

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I/O Instructions

5-17

Version 3.3

Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.

Clear Instruction

When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the

SCSI Output Control Latch (SOCL)

register. Do not set

SACK/ or SATN/ except for testing purposes. When the
target bit is cleared, the corresponding bit in the

SCSI Control Zero (SCNTL0)

register is cleared. When

the carry bit is cleared, the corresponding bit in the ALU
is cleared.

Note:

None of the signals are cleared on the SCSI bus in the
target mode.

Initiator Mode

Select Instruction

The LSI53C896 arbitrates for the SCSI bus by asserting
the SCSI ID stored in the

SCSI Chip ID (SCID)

register.

If it loses arbitration, it tries again during the next
available arbitration cycle without reporting any lost
arbitration status.

If the LSI53C896 wins arbitration, it attempts to select the
SCSI device whose ID is defined in the destination ID
field of the instruction. When the LSI53C896 wins
arbitration, it fetches the next instruction from the address
pointed to by the

DMA SCRIPTS Pointer (DSP)

register.

This way the SCRIPTS can move to the next instruction
before the selection completes. It continues executing
SCRIPTS until a SCRIPTS that requires a response from
the target is encountered.

If the LSI53C896 is selected or reselected before winning
arbitration, it fetches the next instruction from the address
pointed to by the 32-bit jump address field stored in the

OPC2

OPC1

OPC0

Instruction Defined

0

0

0

Select

0

0

1

Wait Disconnect

0

1

0

Wait Reselect

0

1

1

Set

1

0

0

Clear