Avago Technologies LSI53C896 User Manual
Page 62
2-34
Functional Description
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
register, then the least significant byte or the most significant
byte in the SODR register is full.
2.2.13.3 Asynchronous SCSI Receive
Step 1.
If the DMA FIFO size is set to 112 bytes (bit 5 of the
register cleared), look at the DFIFO
and
registers and calculate whether
there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DBC register from
the 7-bit value of the
register. AND the
result with 0x7F for a byte count between zero and 112.
If the DMA FIFO size is set to 944 bytes (bit 5 of the
register is set), subtract the 10 least
significant bits of the
register from
the 10-bit value of the DMA FIFO Byte Offset Counter, which
consists of bits [1:0] in the CTEST5 register and bits [7:0] of the
register. AND the result with 0x3FF for a
byte count between zero and 944.
Step 2.
Read bit 7 in the
and
registers to determine whether any
bytes are left in the
register. If
bit 7 is set in the SSTAT0 or SSTAT2 registers, then the least
significant byte or the most significant byte is full.
Step 3.
If any wide transfers have been performed using the
Chained Move instruction, read the Wide SCSI Receive bit
(
, bit 0) to determine whether a
byte is left in the
register.
2.2.13.4 Synchronous SCSI Receive
Step 1.
If the DMA FIFO size is set to 112 bytes, subtract the seven
least significant bits of the
register
from the 7-bit value of the
register. AND
the result with 0x7F for a byte count between zero and 112.
If the DMA FIFO size is set to 944 bytes (bit 5 of the
register is set), subtract the 10 least
significant bits of the
register from
the 10-bit value of the DMA FIFO Byte Offset Counter, which
consists of bits [1:0] in the CTEST5 register and bits [7:0] of the