Avago Technologies LSI53C896 - Manual (Page 358)

IX-8 Index
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
memory move 5-35
read/write instruction 5-23
transfer control instruction 5-27
INT_DIR 3-10
INTA routing enable 3-22
INTA, INTB disable (IRQD) 4-74
INTA/ 2-43 , 2-46 , 2-49 , 3-10 , 3-22
INTB/ 2-43 , 2-46 , 2-49 , 3-10 , 3-22
interface
128, 256, 512 Kbyte or 1 Mbyte
150 ns memory B-3
16 Kbyte
200 ns memory B-1
512 Kbyte
150 ns memory B-4
64 Kbyte
150 ns memory B-2
control signals 3-7
internal
arbiter 2-11
SCRIPTS RAM 2-21
internal RAM
see also SCRIPTS RAM 2-21
interrupt
A 3-10
acknowledge command 2-5
B 3-10
direction 3-10
handling 2-43
instruction 5-29
line 4-14
on-the-fly (IN) 5-31
on-the-fly (INTF) 4-52
output 6-14
pin (IP) 4-15
request 2-43
routing mode (IRM[1:0]) 4-94
signals 3-10
status one (ISTAT1) 2-43 , 4-53
status zero (ISTAT0) 2-43 , 4-50
interrupt-on-the-fly instruction 5-29
interrupts 2-45
fatal vs. nonfatal interrupts 2-45
halting 2-48
masking 2-46
sample interrupt service routine 2-49
stacked interrupts 2-47
IRDY/ 3-7
IRQ mode (IRQM) 4-74
issuing cache commands 2-12
J
JTAG boundary scan testing 2-26
jump
address 5-33
call a relative address 5-30
call an absolute address 5-30
control (PMJCTL) 4-102
if true/false 5-31
instruction 5-27
JUMP64 address 5-33
L
last disconnect (LDSC) 4-49
latched SCSI parity
(SDP0L) 4-47
for SD[15:8] (SPL1) 4-49
latency 2-10
timer (LT) 4-8
LED_CNTL (LEDC) 4-86
load and store instructions
prefetch unit and store instructions 2-25
load/store 5-39
load/store instructions 2-25 , 5-37
loopback enable 2-26
lost arbitration (LOA) 4-45
LSI53C700 family compatibility (COM) 4-74
LSI53C896
329 ball grid array 6-70
329 BGA mechanical drawing 6-71
new features 1-3
register map A-1
LVD
driver SCSI signals 6-3
receiver SCSI signals 6-3
SCSI 1-4
LVDlink 1-1 , 1-5
benefits 1-5
operation 2-35
M
MAD
bus 2-56
bus programming 3-22
pins 2-56
MAD[0] 3-23
MAD[3:1] 3-23
MAD[4] 3-22
MAD[5] 3-22
MAD[6] 3-22
MAD[7:0] 3-19 , 3-22
MAD[7] 3-22