Avago Technologies LSI53C896 - Manual (Page 217)

SCSI Registers 4-105
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x58–0x59
SCSI Bus Data Lines (SBDL)
Read Only
SBDL SCSI Bus Data Lines [15:0]
This register contains the SCSI data bus status. Even
though the SCSI data bus is active LOW, these bits are
active HIGH. The signal status is not latched and is a true
representation of exactly what is on the data bus at the
time the register is read. This register is used when
receiving data using programmed I/O. This register can
also be used for diagnostic testing or in the low level mode.
The power-up value of this register is indeterminate.
If the chip is in the wide mode
(
SCSI Control Three (SCNTL3) , bit 3 and
SCSI Test Two (STEST2) , bit 2 are set) and
SCSI Bus Data Lines (SBDL) is read, both byte lanes are
checked for parity regardless of phase. When in a
nondata phase, this causes a parity error interrupt to be
generated because upper byte lane parity is invalid.
Registers: 0x5A–0x5B
Reserved
15 0
SBDL
x x x x x x x x x x x x x x x x