Avago Technologies LSI53C896 User Manual
Page 333
SCSI Timing Diagrams
6-65
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Table 6.47
Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock
1
1. Transfer period bits (bits [6:4] in the
register) are set to zero and the
Extra Clock Cycle of Data Setup bit (bit 7 in
) is set.
Symbol
Parameter
2
2. Note: for fast SCSI, set the TolerANT Enable bit (bit 7 in
). During Ultra
SCSI transfers, the value of the Extend REQ/ACK Filtering bit (
, bit 1) has
no effect.
Min
Max
Unit
t
1
Send SREQ/ or SACK/ assertion pulse width
16
–
ns
t
2
Send SREQ/ or SACK/ deassertion pulse width
16
–
ns
t
1
Receive SREQ/ or SACK/ assertion pulse width
10
–
ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width
10
–
ns
t
3
Send data setup to SREQ/ or SACK/ asserted
12
–
ns
t
4
Send data hold from SREQ/ or SACK/ asserted
17
–
ns
t
5
Receive data setup to SREQ/ or SACK/ asserted
0
–
ns
t
6
Receive data hold from SREQ/ or SACK/ asserted
6
–
ns
Table 6.48
Ultra SCSI HVD Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes
(16-Bit Transfers) 80 MHz Clock
1
1. Transfer period bits (bits [6:4] in the
register) are set to zero and the
Extra Clock Cycle of Data Setup bit (bit 7 in
) is set.
Symbol
Parameter
2
2. During Ultra SCSI transfers, the value of the Extend REQ/ACK Filtering bit (
bit 1) has no effect.
Min
Max
Unit
t
1
Send SREQ/ or SACK/ assertion pulse width
16
–
ns
t
2
Send SREQ/ or SACK/ deassertion pulse width
16
–
ns
t
1
Receive SREQ/ or SACK/ assertion pulse width
10
–
ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width
10
–
ns
t
3
Send data setup to SREQ/ or SACK/ asserted
16
–
ns
t
4
Send data hold from SREQ/ or SACK/ asserted
21
–
ns
t
5
Receive data setup to SREQ/ or SACK/ asserted
0
–
ns
t
6
Receive data hold from SREQ/ or SACK/ asserted
6
–
ns