Mailbox zero (mbox0), Register: 0x16 – Avago Technologies LSI53C896 User Manual

Page 166

4-54

Registers

Version 3.3

SRUN

SCRIPTS Running

This bit indicates whether or not the SCRIPTS engine is
currently fetching and executing SCRIPTS instructions. If
this bit is set, the SCRIPTS engine is active.

If it is cleared, the SCRIPTS engine is not active.

This bit is read-only, and writes have no effect on the
value of this bit.

SYNC_IRQD

Setting this bit disables the INTA/ pin for Function A and the
INTB/ pin for Function B. Clearing this bit enables normal
operation of the INTA/ (or INTB/) pin. The function of this
bit is nearly identical to bit 1 of

DMA Control (DCNTL)

(Register

0x3B

) except that if the INTA/ (or INTB/) is

already asserted and this bit is set, INT remains asserted
until the interrupt is serviced. At this point the interrupt line
is blocked for future interrupts until this bit is cleared. In
addition, this bit may be read and written while SCRIPTS
are executing.

Register: 0x16

Mailbox Zero (MBOX0)
Read/Write

MBOX0

Mailbox Zero

[7:0]

These are general purpose bits that may be read or
written while SCRIPTS are running. They also may be
read or written by the SCRIPTS processor.

Note:

The host and the SCRIPTS processor code could
potentially attempt to access the same mailbox byte at the
same time. Using one mailbox register as a read only and
the other as a write only prevents this type of conflict.

MBOX0