Avago Technologies LSI53C896 - Manual (Page 330)

6-62 Specifications
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.38 Target Asynchronous Receive
Table 6.42 Target Asynchronous Receive
Symbol Parameter Min Max Unit
t
1
SREQ/ deasserted from SACK/ asserted 5 – ns
t
2
SREQ/ asserted from SACK/ deasserted 5 – ns
t
3
Data setup to SACK/ asserted 0 – ns
t
4
Data hold from SREQ/ deasserted 0 – ns
Valid n Valid n + 1
n + 1
n + 1
n
n
t
1
t
2
t
3 t
4
SREQ/
SACK/
SD[15:0]/,
SDP[1:0]/