Avago Technologies LSI53C896 - Manual (Page 25)

LSI53C896 Benefits Summary 1-7
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
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Includes 8 Kbytes of internal RAM for SCRIPTS instruction storage
for each SCSI channel.
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31 levels of SCSI synchronous offset.
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Supports variable block size and scatter/gather data transfers.
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Performs sustained memory-to-memory DMA transfers to
approximately 100 Mbytes/s.
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Minimizes SCSI I/O start latency.
•
Performs complex bus sequences without interrupts, including
restoring data pointers.
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Reduces ISR overhead through a unique interrupt status reporting
method.
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Load/Store SCRIPTS instructions increase performance of data
transfers to and from the chip registers without using PCI cycles.
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SCRIPTS support of 64-bit addressing.
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Supports target disconnect and later reconnect with no interrupt to
the system processor.
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Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.
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Expanded Register Move instruction supports additional
arithmetic capability.
1.5.2 PCI Performance
The LSI53C896:
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Complies with the PCI 2.1 specification.
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64-bit or 32-bit 33 MHz PCI interface.
– Dual Address Cycle (DAC) can be generated for all SCRIPTS.
– True PCI Multifunction Device – presents one electrical load to
the PCI Bus.
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Bursts 2/4, 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers
across the PCI bus.
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Supports 64-bit or 32-bit word data bursts with variable burst lengths.
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Prefetches up to 8 Dwords of SCRIPTS instructions.
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Bursts SCRIPTS opcode fetches across the PCI bus.