Avago Technologies LSI53C896 - Manual (Page 172)

4-60 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
During any Memory-to-Memory Move operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
Register: 0x20
DMA FIFO (DFIFO)
Read/Write
BO Byte Offset Counter [7:0]
These bits, along with bits [1:0] in the
Chip Test Five (CTEST5) register, indicate the amount of
data transferred between the SCSI core and the DMA
core. It determines the number of bytes in the DMA FIFO
when an interrupt occurs. These bits are unstable while
data is being transferred between the two cores. When the
chip has stopped transferring data, these bits are stable.
The DMA FIFO (DFIFO) register counts the number of
bytes transferred between the DMA core and the SCSI
core. The
DMA Byte Counter (DBC) register counts the
number of bytes transferred across the host bus. The
difference between these two counters represents the
number of bytes remaining in the DMA FIFO.
The following steps determine how many bytes are left in
the DMA FIFO when an error occurs, regardless of the
transfer direction:
If the DFS bit (bit 5, Chip Test Five (CTEST5) ) is set:
Step 1.Subtract the ten least significant bits of the
DMA Byte Counter (DBC) register from the
10-bit value of the DFBOC which is made up of
the
Chip Test Five (CTEST5) register (bits [1:0])
and the DMA FIFO (DFIFO) register (bits [7:0]).
Step 2.AND the result with 0x3FF for a byte count
between zero and 944.
If the DFS bit (bit 5, Chip Test Five (CTEST5) ) is cleared:
7 0
BO
0 0 0 0 0 0 0 1