Avago Technologies LSI53C896 - Manual (Page 360)

IX-10 Index
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
interface signals 3-5
master transaction 2-12
master transfer 2-12
memory space 2-4
performance 1-7
target disconnect 2-10
target retry 2-10
PERR/ 3-9
phase mismatch
handling in SCRIPTS 2-20
jump address 1 (PMJAD1) 4-111
jump address 2 (PMJAD2) 4-111
jump registers 4-111
physical dword address and data 3-6
PME
clock (PMEC) 4-17
enable (PEN) 4-18
status (PST) 4-18
support (PMES) 4-17
polling 2-43
power
and ground signals 3-21
management 2-58
capabilities 4-17
control/status 4-18
state (PWS[1:0]) 4-18
state D0 2-59
state D1 2-59
state D2 2-60
state D3 2-60
prefetch
enable (PFEN) 4-73
flush 2-25
flush (PFF) 4-72
SCRIPTS instructions 2-24
pull-ups, internal, conditions 3-4
R
RAM, see also SCRIPTS RAM 2-21
RBIAS 3-21
read
line 2-11 , 2-12
line function 2-8
modify-write cycles 5-24
multiple 2-9 , 2-11 , 2-12
multiple with read line enabled 2-9
write instructions 5-23
write system memory from SCRIPTS 5-35
read/write
instructions 5-23 , 5-25
system memory from SCRIPTS 5-35
received
master abort (from master) (RMA) 4-5
target abort (from master) (RTA) 4-5
register
address 5-39
address - A[6:0] 5-23
register map A-1
registers 2-43
relative 5-20
relative addressing mode 5-19 , 5-30
remaining byte count (RBC) 4-112
REQ/ 2-11 , 3-8
REQ/ - GNT/ 2-3
REQ64/ 3-7
request 3-8
request 64 3-7
reselect 2-20
during reselection 2-40
instruction 5-15
reselected (RSL) 2-45 , 4-76 , 4-80
reserved command 2-6
reset 3-5
input 6-13
SCSI offset (ROF) 4-95
response ID one (RESPID1) 4-91
response ID zero (RESPID0) 4-91
return instruction 5-28
revision ID register 4-6
(RID) 4-6
rise and fall time test condition 6-9
ROM
interface 2-55
pin 2-57
RST/ 3-5
S
SACK 2-48
SACs 2-22
SCLK 3-13
quadrupler enable (QEN) 4-94
quadrupler select (QSEL) 4-94
scratch
byte register (SBR) 4-72
register A (SCRATCHA) 4-68
register B (SCRATCHB) 4-106
registers C–R (SCRATCHC–SCRATCHR) 4-106
script fetch selector (SFS) 4-108
SCRIPTS
instruction 2-53
interrupt instruction received (SIR) 4-42 , 4-71
processor 2-20
internal RAM for instruction storage 2-21
performance 2-20