Avago Technologies LSI53C896 User Manual
Page 82
2-54
Functional Description
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.2.19.3 SWIDE Register
This register stores data for partial byte data transfers. For receive data,
the
register holds the high-order byte of a
partial SCSI transfer that has not yet been transferred to memory. This
stored data may be a residue byte (and therefore ignored) or it may be
valid data that is transferred to memory at the beginning of the next
Block Move instruction.
2.2.19.4 SODL Register
For send data, the low-order byte of the
register holds the low-order byte of a partial memory transfer that has
not yet been transferred across the SCSI bus. This stored data is usually
“married” with the first byte of the next data send transfer, and both bytes
are sent across the SCSI bus at the start of the next data send block
move command.
2.2.19.5 Chained Block Move SCRIPTS Instruction
A chained Block Move SCRIPTS instruction primarily transfers
consecutive data send or data receive blocks. Using the chained
Block Move instruction facilitates partial receive transfers and allows
correct partial send behavior without additional opcode overhead.
Behavior of the chained Block Move instruction varies slightly for sending
and receiving data.
For receive data (Data-In for the initiator or Data-Out for the target), a
chained Block Move instruction indicates that if a partial transfer occurred
at the end of the instruction, the WSR flag is set. The high-order byte of
the last SCSI transfer is stored in the
register rather than transferred to memory. The contents of the SWIDE
register should be the first byte transferred to memory at the start of the
chained Block Move data stream. Because the byte count always
represents data transfers to/from memory (as opposed to the SCSI bus),
the byte transferred out of the
register is
one of the bytes in the byte count. If the WSR bit is cleared when a
receive data chained Block Move instruction is executed, the data
transfer occurs similar to that of the regular Block Move instruction.
Whether the WSR bit is set or cleared, when a normal block move
instruction is executed, the contents of the SWIDE register are ignored