Interrupt status zero (istat0), Data structure address (dsa), Register: 0x14 – Avago Technologies LSI53C896 User Manual
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Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x10–0x13
Data Structure Address (DSA)
Read/Write
DSA
Data Structure Address
[31:0]
This 32-bit register contains the base address used for all
table indirect calculations. The DSA register is usually
loaded prior to starting an I/O, but it is possible for a
SCRIPTS Memory Move to load the DSA during the I/O.
During any Memory-to-Memory Move operation, the
contents of this register is preserved. The power-up value
of this register is indeterminate.
Register: 0x14
Interrupt Status Zero (ISTAT0)
Read/Write
This is the only register that is accessible by the host CPU while an
LSI53C896 SCSI function is executing SCRIPTS (without interfering in
the operation of the function). It polls for interrupts if hardware interrupts
are disabled. Read this register after servicing an interrupt to check for
stacked interrupts.
ABRT
Aborted
7
Setting this bit aborts the current operation under
execution by the LSI53C896 SCSI function. If this bit is
set and an interrupt is received, clear this bit before
reading the
register to prevent
further aborted interrupts from being generated. The
sequence to abort any operation is:
1.Set this bit.
2.Wait for an interrupt.
3.Read the
Interrupt Status Zero (ISTAT0)
register.
31
0
DSA
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
ABRT
SRST
SIGP
SEM
CON
INTF
SIP
DIP
0
0
0
0
0
0
0
0