4 phase mismatch jump registers, Phase mismatch jump registers, Phase mismatch jump address 1 (pmjad1) – Avago Technologies LSI53C896 User Manual
Page 223: Phase mismatch jump address 2 (pmjad2), Section 4.4, “phase mismatch jump registers, Registers: 0xc0–0xc3, Registers: 0xc4–0xc7
Phase Mismatch Jump Registers
4-111
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
4.4 Phase Mismatch Jump Registers
Eight 32-bit registers contain the byte count and addressing information
required to update the direct, indirect, or table indirect BMOV instructions
with new byte counts and addresses. The eight register descriptions follow.
All registers can be read/written using the Load/Store SCRIPTS
instructions, Memory-to-Memory Moves, read/write SCRIPTS
instructions, or the CPU with SCRIPTS not running.
Registers: 0xC0–0xC3
Phase Mismatch Jump Address 1 (PMJAD1)
Read/Write
PMJAD1
Phase Mismatch Jump Address 1
[31:0]
This register contains the 32-bit address that is jumped
to upon a phase mismatch. Depending upon the state of
the PMJCTL bit this address is used either during an
outbound (data out, command, message out) phase
mismatch (PMJCTL = 0) or when the WSR bit is cleared
(PMJCTL = 1). It should be loaded with an address of a
SCRIPTS routine that handles the updating of memory
data structures of the BMOV that was executing when the
phase mismatch occurred.
Registers: 0xC4–0xC7
Phase Mismatch Jump Address 2 (PMJAD2)
Read/Write
PMJAD2
Phase Mismatch Jump Address 2
[31:0]
This register contains the 32-bit address that is jumped
to upon a phase mismatch. Depending upon the state of
the PMJCTL bit this address is used either during an
31
0
PMJAD1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
PMJAD2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0