Avago Technologies LSI53C896 User Manual
Page 239
Block Move Instructions
5-11
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
The LSI53C896 verifies that it is connected to the SCSI
bus as a target before executing this instruction.
The LSI53C896 asserts the SCSI phase signals (SMSG/,
SC_D/, and SI_O/) as defined by the Phase Field bits in
the instruction.
If the instruction is for the command phase, the
LSI53C896 receives the first command byte and decodes
its SCSI Group Code.
•
If the SCSI Group Code is either Group 0, Group 1,
Group 2, or Group 5, then the LSI53C896 overwrites
the
register with the length
of the Command Descriptor Block: 6, 10, or 12 bytes.
•
If the Vendor Unique Enhancement 0 (VUE0) bit
(
, bit 1) is cleared and the
SCSI group code is a vendor unique code, the
LSI53C896 overwrites the
register with the length of the Command Descriptor
Block: 6, 10, or 12 bytes. If the VUE0 bit is set, the
LSI53C896 receives the number of bytes in the byte
count regardless of the group code.
•
If any other Group Code is received, the
register is not modified and
the LSI53C896 requests the number of bytes
specified in the
register. If
the DBC register contains 0x000000, an illegal
instruction interrupt is generated.
The LSI53C896 transfers the number of bytes specified
in the
register starting at the
address specified in the
register. If the Opcode bit is set and a data transfer ends
on an odd byte boundary, the LSI53C896 stores the last
byte in the
register during
a receive operation. This byte is combined with the first
byte from the subsequent transfer so that a wide transfer
can complete.
If the SATN/ signal is asserted by the initiator or a parity
error occurred during the transfer, it is possible to halt the
transfer and generate an interrupt. The Disable Halt on
Parity Error or ATN bit in the
register controls whether the LSI53C896 halts on these
conditions immediately, or waits until completion of the
current Move.