Avago Technologies LSI53C896 - Manual (Page 92)

3-4 Signal Descriptions
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
3.1 Internal Pull-ups on LSI53C896 Signals
Several LSI53C896 signals use internal pull-ups and pull-downs.
Table 3.1 describes the conditions that enable these pull-ups and
pull-downs.
Table 3.1 LSI53C896 Internal Pull-ups and Pull-downs
Pin Name
Pull-up
Current (
µ
A) Conditions for Pull-up
INTA/, INTB/, ALT_INTA/,
ALT_INTB/ 25 Pull-up enabled when the “AND-tree” mode is
enabled by driving TEST_RST/ LOW or when the
IRQ mode bit (bit 3 of DCNTL, 0X3B) is cleared.
1
INT_DIR, TCK, TDI,
TEST_RST/, TMS 25 Pulled up internally.
AD[63:32], C_BE[7:4], PAR64 25 Pulled up internally if not used.
GPIO[4:0]
−
25 Pulled down internally when configured as inputs.
MAD[7:0]
−
25 Pulled down internally.
TDO, TEST_HSC
−
25 Pulled down internally.
1. When bit 3 of DMA Control (DCNTL) is set, the pad becomes a totem pole output pad and drives
both HIGH and LOW.