Avago Technologies LSI53C896 User Manual

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Functional Description

Version 3.3

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The part must be doing a PCI Master transfer. The following PCI
Master transactions do not utilize the PCI cache logic and thus no
PCI cache commands are issued during these types of cycles: a
nonprefetch SCRIPTS fetch, a Load/Store data transfer, a data flush
operation. All other types of PCI Master transactions utilize the PCI
cache logic.

These conditions must be met for the cache logic to control the type of
PCI cache command that is issued, along with any alignment that may
be necessary during write operations. If these conditions are not met for
any given PCI Master transaction, a Memory Read or Memory Write is
issued and no cache write alignment is done.

2.1.4.2 Issuing Cache Commands

To issue each type of PCI cache command, the corresponding enable bit
must be set (2 bits in the case of Memory Write and Invalidate).

•

To issue Memory Read Line commands, set the Memory Read Line
enable bit in the

DMA Mode (DMODE)

•

To issue Memory Read Multiple commands, set the Read Multiple
enable bit in the

DMA Mode (DMODE)

•

To issue Memory Write and Invalidate commands, set the Write and
Invalidate enables in both the

Chip Test Three (CTEST3)

and the

PCI configuration Command registers.

If the corresponding cache command that is to be issued is not enabled,
the cache logic falls back to the next command enabled – that is, if
Memory Read Multiple is not enabled and Memory Read Lines are
enabled, read lines are issued in place of read multiples. If no cache
commands are enabled, cache write alignment still occur but no cache
commands are issued; only memory reads and memory writes are issued.

2.1.4.3 Memory Read Caching

Which type of Memory Read command gets issued depends on the
starting location of the transfer and the number of bytes to be transferred.
During reads, no cache alignment is done (this is not required nor
optimal according to the PCI 2.1 specification) and reads are always a
programmed burst length, as set in the

DMA Mode (DMODE)

and

Chip Test Three (CTEST3)

registers. In the case of a transfer that is