Avago Technologies LSI53C896 - Manual (Page 357)

Index IX-7
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
even parity 2-27
expansion ROM base address 2-56 , 2-57 , 4-13
extend SREQ/SACK filtering (EXT) 4-96
external
clock 6-12
memory interface 2-56
configuration 2-56
diagram examples B-1
multiple byte accesses 6-14
slow memory 2-57
memory timing 6-38
memory write 6-43
extra clock cycle of data setup (EXC) 4-24
F
fetch
enable (FE) 4-86
pin mode (FM) 4-59
FIFO
byte control (FBL[2:0]) 4-62
byte control (FBL3) 4-61
flags (FF[3:0]) 4-46
flags, bit 4 (FF4) 4-49
first dword 5-5 , 5-15 , 5-23 , 5-27 , 5-38
flash ROM and memory interface signals 3-19
flush DMA FIFO (FLF) 4-58
flushing (FLSH) 4-53
FRAME/ 3-7
frequency lock (LOCK) 4-100
full arbitration, selection/reselection 4-22
function complete 2-45
(CMP) 4-76 , 4-80
G
general description 1-1
general purpose
(GPREG) 4-37
I/O (GPIO) 4-38
I/O pin 0 3-11 , 3-12
I/O pin 1 3-11 , 3-12
I/O pin 2 3-11 , 3-12
I/O pin 3 3-11 , 3-12
I/O pin 4 3-11 , 3-12
pin control (GPCNTL) 4-85
timer expired (GEN) 2-45 , 4-78 , 4-82
timer period (GEN[3:0]) 4-90
timer scale factor (GENSF) 4-88
GNT/ 2-11 , 3-8
GPIO enable (GPIO[1:0]) 4-86
GPIO enable (GPIO[4:2]) 4-86
grant 3-8
H
halt SCSI clock (HSC) 4-97
halting 2-48
handshake-to-handshake
timer bus activity enable (HTHBA) 4-88
timer expired (HTH) 2-45 , 4-79 , 4-82
timer period (HTH[3:0]) 4-87
timer scale factor (HTHSF) 4-90
hardware control of SCSI activity LED 2-22
hardware interrupts 2-43
header type (HT) 4-8
high impedance mode (ZMOD) 4-103
high voltage differential interface 2-38
high voltage differential mode
autoswitching with LVD and single-ended mode 2-35
description 2-36
HVD or SE/LVD (DIF) 4-95
HVD signals 2-36
I
I/O 3-3
instructions 5-15
read command 2-6
space 2-4
write command 2-6
IDSEL 2-3 , 3-8
signal 2-6
illegal instruction detected (IID) 4-43 , 4-71
immediate
arbitration (IARB) 4-26
data 5-24
indirect addressing 5-5
initialization device select 3-8
initiator
asynchronous receive 6-61
asynchronous send 6-60
mode 5-12 , 5-17
phase mismatch 4-79
ready 3-7
synchronous transfer 6-66
timing 6-22
input 3-3
capacitance 6-4
current as a function of input voltage 6-10
signals 6-6
instruction
address (IA) 4-114
prefetch unit flushing 2-24
type 5-38
block move 5-5
I/O instruction 5-15