beautypg.com

External memory read (cont.) – Avago Technologies LSI53C896 User Manual

Page 309

background image

PCI and External Memory Interface Timing Diagrams

6-41

Version 3.3

Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.

Figure 6.25 External Memory Read (Cont.)

CLK

(Driven by System)

PAR

(Driven by

Master

-Addr;

IRDY/

(Driven by Master)

TRDY/

(Driven by LSI53C896)

STOP/

(Driven by LSI53C896)

DEVSEL/

(Driven by LSI53C896)

AD[31:0]

(Driven by Master-Addr;

C_BE[3:0]/

(Driven by Master)

FRAME/

(Driven by Master)

Data Driven by Memory)

11

12

13

14

15

16

17

18

19

20

LSI53C896-Data)

Data

Out

LSI53C896-Data)

MAD

(Addr drvn by LSI53C896;

MAS1/

(Driven by LSI53C896)

MAS0/

(Driven by LSI53C896)

MCE/

(Driven by LSI53C896)

MOE/

(Driven by LSI53C896)

MWE/

(Driven by LSI53C896)

t

3

t

2

t

2

t

15

21

t

3

Out

t

3

t

3

Data

In

t

19

t

17

t

14

t

16