Scsi control three (scntl3), Register: 0x03 – Avago Technologies LSI53C896 User Manual
Page 142
4-30
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x03
SCSI Control Three (SCNTL3)
Read/Write
USE
Ultra SCSI Enable
7
Setting this bit enables Ultra SCSI or Ultra2 SCSI
synchronous transfers. The default value of this bit is 0.
This bit should remain cleared if the LSI53C896 is not
operating in Ultra SCSI mode or faster.
When this bit is set, the signal filtering period for SREQ/
and SACK/ automatically changes to 8 ns for Ultra2 SCSI
or 15 ns for Ultra SCSI, regardless of the value of the
Extend REQ/ACK Filtering bit in the
register.
Note:
Set this bit to achieve Ultra SCSI transfer rates in legacy
systems that use an 80 MHz clock.
SCF[2:0]
Synchronous Clock Conversion Factor
[6:4]
These bits select a factor by which the frequency of SCLK
is divided before being presented to the synchronous
SCSI control logic. Write these to the same value as the
following Clock Conversion Factor bits unless fast SCSI
operation is desired. Refer to the
register description for examples of how the SCF bits
calculate synchronous transfer periods. Refer to the table
under the description of bits [7:5] of the SXFER register
for the valid combinations.
EWS
Enable Wide SCSI
3
When this bit is cleared, all information transfer phases
are assumed to be eight bits, transmitted on SD[7:0]/ and
SDP0/. When this bit is asserted, data transfers are done
16 bits at a time, with the least significant byte on
SD[7:0]/ and SDP0/ and the most significant byte on
SD[15:8]/, SDP1/. Command, Status, and Message
phases are not affected by this bit.
7
6
4
3
2
0
USE
SCF[2:0]
EWS
CCF[2:0]
0
0
0
0
0
0
0
0