If bit 5 is set in the SSTAT0 or SSTAT2 register, then the least
significant byte or the most significant byte in the SODL register
is full. Checking this bit also reveals bytes left in the SODL
register from a Chained Move operation with an odd byte count.

2.2.13.2 Synchronous SCSI Send

Step 1.

If the DMA FIFO size is set to 112 bytes (bit 5 of the

Chip Test Five (CTEST5)

DMA FIFO (DFIFO)

and

DMA Byte Counter (DBC)

registers and

calculate whether there are bytes left in the DMA FIFO. To make
this calculation, subtract the seven least significant bits of the
DBC register from the 7-bit value of the DFIFO register. AND
the result with 0x7F for a byte count between zero and 112.

If the DMA FIFO size is set to 944 bytes (bit 5 of the

Chip Test Five (CTEST5)

significant bits of the

DMA Byte Counter (DBC)

the 10-bit value of the DMA FIFO Byte Offset Counter, which
consists of bits [1:0] in the

Chip Test Five (CTEST5)

and bits [7:0] of the

DMA FIFO (DFIFO)

with 0x3FF for a byte count between zero and 944.

Step 2.

Read bit 5 in the

SCSI Status Zero (SSTAT0)

and

SCSI Status Two (SSTAT2)

registers to determine whether any

bytes are left in the SODL register. If bit 5 is set in the SSTAT0
or SSTAT2 register, then the least significant byte or the most
significant byte in the

SCSI Output Data Latch (SODL)

is full. Checking this bit also reveals bytes left in the SODL
register from a Chained Move operation with an odd byte count.

Step 3.

Read bit 6 in the

SCSI Status Zero (SSTAT0)

and

SCSI Status Two (SSTAT2)

registers to determine whether any

bytes are left in the SODR register (a hidden buffer register that
is not accessible). If bit 6 is set in the SSTAT0 or SSTAT2