Avago Technologies LSI53C896 - Manual (Page 188)

4-76 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x40
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status Zero (SIST0)
register. An interrupt is masked by clearing the appropriate mask bit. For
details on interrupts refer to
Chapter 2, “Functional Description.”
M/A SCSI Phase Mismatch – Initiator Mode;
SCSI ATN Condition – Target Mode
7
In the initiator mode, this bit is set when the SCSI phase
asserted by the target and sampled during SREQ/ does
not match the expected phase in the
SCSI Output Control Latch (SOCL) register. This expected
phase is automatically written by SCSI SCRIPTS. In the
target mode, this bit is set when the initiator asserts
SATN/. Refer to the Disable Halt on Parity Error or
SATN/ Condition bit in the
SCSI Control One (SCNTL1)
register for details on when this status is raised.
CMP Function Complete 6
Indicates full arbitration and selection sequence is
completed.
SEL Selected 5
Indicates the LSI53C896 SCSI function is selected by a
SCSI initiator device. Set the Enable Response to Selection
bit in the
SCSI Chip ID (SCID) register for this to occur.
RSL Reselected 4
Indicates the LSI53C896 SCSI function is reselected by
a SCSI target device. Set the Enable Response to
Reselection bit in the
SCSI Chip ID (SCID) register for
this to occur.
7 6 5 4 3 2 1 0
M/A CMP SEL RSL SGE UDC RST PAR
0 0 0 0 0 0 0 0