Avago Technologies LSI53C896 - Manual (Page 11)

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Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
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1.1 Typical LSI53C896 System Application 1-2
1.2 Typical LSI53C896 Board Application 1-3
2.1 LSI53C896 Block Diagram 2-2
2.2 Parity Checking/Generation 2-30
2.3 DMA FIFO Sections 2-31
2.4 LSI53C896 Host Interface SCSI Data Paths 2-32
2.5 8-Bit HVD Wiring Diagram for Ultra SCSI 2-37
2.6 Regulated Termination for Ultra2 SCSI 2-39
2.7 Determining the Synchronous Transfer Rate 2-41
2.8 Interrupt Routing Hardware Using the LSI53C896 2-51
2.9 Block Move and Chained Block Move Instructions 2-52
3.1 LSI53C896 Functional Signal Grouping 3-2
5.1 SCRIPTS Overview 5-4
5.2 Block Move Instruction – First Dword 5-5
5.3 Block Move Instruction – Second Dword 5-14
5.4 Block Move Instruction – Third Dword 5-14
5.5 First 32-Bit Word of the I/O Instruction 5-15
5.6 Second 32-Bit Word of the I/O Instruction 5-22
5.7 Read/Write Instruction – First Dword 5-23
5.8 Read/Write Instruction – Second Dword 5-24
5.9 Transfer Control Instructions – First Dword 5-27
5.10 Transfer Control Instructions – Second Dword 5-33
5.11 Transfer Control Instructions – Third Dword 5-33
5.12 Memory Move Instructions – First Dword 5-35
5.13 Memory Move Instructions – Second Dword 5-36
5.14 Memory Move Instructions – Third Dword 5-37
5.15 Load/Store Instruction – First Dword 5-38
5.16 Load/Store Instructions – Second Dword 5-40
6.1 LVD Driver 6-3
6.2 LVD Receiver 6-4
6.3 Rise and Fall Time Test Condition 6-9
6.4 SCSI Input Filtering 6-9
6.5 Hysteresis of SCSI Receivers 6-10
6.6 Input Current as a Function of Input Voltage 6-10
6.7 Output Current as a Function of Output Voltage 6-11
6.8 External Clock 6-12