Avago Technologies LSI53C896 User Manual
Page 70
2-42
Functional Description
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.2.16.3
Register, Bits [2:0] (CCF[2:0])
The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the asynchronous SCSI core logic. This
divider must be set according to the input clock frequency in the table.
2.2.16.4
Register, Bits [7:5] (TP[2:0])
The TP[2:0] divider bits determine the SCSI synchronous transfer period
when sending synchronous SCSI data in either the initiator or target
mode. This value further divides the output from the SCF divider.
2.2.16.5 Ultra2 SCSI Synchronous Data Transfers
Ultra2 SCSI is an extension of the current Ultra SCSI synchronous
transfer specifications. It allows synchronous transfer periods to be
negotiated down as low as 25 ns, which is half the 50 ns period allowed
under Ultra SCSI. This allows a maximum transfer rate of 80 Mbytes/s
on a 16-bit, LVD SCSI bus. The LSI53C896 has a SCSI clock quadrupler
that must be enabled for the chip to perform Ultra2 SCSI transfers with
a 40 MHz oscillator. In addition, the following bit values affect the chip’s
ability to support Ultra2 SCSI synchronous transfer rates:
•
Clock Conversion Factor bits,
register
bits [2:0] and Synchronous Clock Conversion Factor bits, SCNTL3
register bits [6:4]. These fields support a value of 111 (binary),
allowing the 160 MHz SCLK frequency to be divided down by 8 for
the asynchronous logic.
•
Ultra2 SCSI Enable bit,
register bit 7.
Setting this bit enables Ultra2 SCSI synchronous transfers in
systems that use the internal SCSI clock quadrupler.
•
TolerANT Enable bit,
register bit 7. Active
negation must be enabled for the LSI53C896 to perform Ultra2
SCSI transfers.
Note:
The clock quadrupler requires a 40 MHz external clock.
LSI Logic software assumes that the LSI53C896 is
connected to a 40 MHz external clock, which is quadrupled
to achieve Ultra2 SCSI transfer rates.