Scsi status zero (sstat0), Register: 0x0d – Avago Technologies LSI53C896 User Manual
Page 156
4-44
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
•
A Memory Move instruction is executed with one of
the reserved bits in the
register set.
•
A Memory Move instruction is executed with the
source and destination addresses not aligned.
Register: 0x0D
SCSI Status Zero (SSTAT0)
Read Only
ILF
SIDL Least Significant Byte Full
7
This bit is set when the least significant byte in the
contains data. Data is
transferred from the SCSI bus to the SCSI Input Data
Latch register before being sent to the DMA FIFO and then
to the host bus. The
register
contains SCSI data received asynchronously. Synchronous
data received does not flow through this register.
ORF
SODR Least Significant Byte Full
6
This bit is set when the least significant byte in the SCSI
Output Data Register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR is
used by the SCSI logic as a second storage register
when sending data synchronously. It is not readable or
writable by the user. It is possible to use this bit to
determine how many bytes reside in the chip when an
error occurs.
OLF
SODL Least Significant Byte Full
5
This bit is set when the least significant byte in the
contains data. The
SODL register is the interface between the DMA logic and
the SCSI bus. In synchronous mode, data is transferred
from the host bus to the
register, and then to the SCSI Output Data Register
(SODR, a hidden buffer register which is not accessible)
before being sent to the SCSI bus. In asynchronous
mode, data is transferred from the host bus to the SODL
7
6
5
4
3
2
1
0
ILF
ORF
OLF
AIP
LOA
WOA
RST
SDP0
0
0
0
0
0
0
0
0