Avago Technologies LSI53C896 User Manual
Page 35
PCI Functional Description
2-7
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.1.2.9 Configuration Write Command
The Configuration Write command transfers data to the configuration
space of each agent. An agent is selected when its IDSEL signal is
asserted and AD[1:0] are 0b00. During the address phase of a
configuration cycle, the AD[7:2] lines address the 64 Dword registers
(where byte enables address the bytes within each Dword) in the
configuration space of each device. AD[63:11] are logical don’t cares to
the selected agent. AD[10:8] indicate which device of a multifunction
agent is addressed.
2.1.2.10 Memory Read Multiple Command
This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The LSI53C896 supports PCI Memory
Read Multiple functionality and issues Memory Read Multiple commands
on the PCI bus when the Read Multiple mode is enabled. This mode is
enabled by setting bit 2 (ERMP) of the
register. If
cache mode is enabled, a Memory Read Multiple command is issued on
all read cycles, except opcode fetches, when the following conditions
are met:
•
The (Cache Line Size Enable (CLSE) bit, bit 7,
register) and the Enable Read Multiple (ERMP) bit (bit 2,
register) are set.
•
The
register for each function contains a legal burst
size value (2, 4, 8, 16, 32, or 64), and that value is less than or equal
to the DMODE burst size.
•
The transfer crosses a cache line boundary.
When these conditions are met, the chip issues a Memory Read Multiple
command instead of a Memory Read during all PCI read cycles.