Avago Technologies LSI53C896 - Manual (Page 267)

Load/Store Instructions 5-39
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
When this bit is set, the chip determines the memory
address to perform the Load/Store to/from by adding the
24 bit signed offset value in the
DMA SCRIPTS Pointer Save (DSPS) to the
Data Structure Address (DSA) .
R Reserved [27:26]
NF No Flush (Store Instruction Only) 25
When this bit is set, the LSI53C896 performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For details on
SCRIPTS instruction prefetching, refer to
Chapter 2, "Functional Description."
LS Load/Store 24
When this bit is set, the instruction is a Load. When
cleared, it is a Store.
A[7:0] Register Address [23:16]
A[7:0] selects the register to load/store to/from within the
LSI53C896.
R Reserved [15:3]
BC Byte Count [2:0]
This value is the number of bytes to load/store.