Avago Technologies LSI53C896 - Manual (Page 153)

SCSI Registers 4-41
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x0B
SCSI Bus Control Lines (SBCL)
Read Only
REQ Assert SCSI REQ/ Signal 7
ACK Assert SCSI ACK/ Signal 6
BSY Assert SCSI BSY/ Signal 5
SEL Assert SCSI SEL/ Signal 4
ATN Assert SCSI ATN/ Signal 3
MSG Assert SCSI MSG/ Signal 2
C_D Assert SCSI C_D/ Signal 1
I_O Assert SCSI I_O/ Signal 0
This register returns the SCSI control line status. A bit is set when the
corresponding SCSI control line is asserted. These bits are not latched;
they are a true representation of what is on the SCSI bus at the time the
register is read. The resulting read data is synchronized before being
presented to the PCI bus to prevent parity errors from being passed to
the system. This register is used for diagnostic testing or operation in the
low level mode.
Register: 0x0C
DMA Status (DSTAT)
Read Only
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register in case additional
interrupts are pending (the LSI53C896 SCSI functions stack interrupts).
7 6 5 4 3 2 1 0
REQ ACK BSY SEL ATN MSG C_D I_O
x x x x x x x x
7 6 5 4 3 2 1 0
DFE MDPE BF ABRT SSI SIR R IID
1 0 0 0 0 0 x 0