Avago Technologies LSI53C896 - Manual (Page 283)

PCI and External Memory Interface Timing Diagrams 6-15
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
– Operating Register/SCRIPTS RAM Read, 64-Bit
– Operating Register/SCRIPTS RAM Write, 32-Bit
– Operating Register/SCRIPTS RAM Write, 64-Bit
•
Initiator Timing
– Nonburst Opcode Fetch, 32-Bit Address and Data
– Burst Opcode Fetch, 32-Bit Address and Data
– Back to Back Read, 32-Bit Address and Data
– Back to Back Write, 32-Bit Address and Data
– Burst Read, 32-Bit Address and Data
– Burst Read, 64-Bit Address and Data
– Burst Write, 32-Bit Address and Data
– Burst Write, 64-Bit Address and Data
•
External Memory Timing
– External Memory Read
– External Memory Write
– Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Read
Cycle
– Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Write
Cycle
– Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Read
Cycle
– Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Write
Cycle
– Slow Memory (
≥
128 Kbytes) Read Cycle
– Slow Memory (
≥
128 Kbytes) Write Cycle
–
≤
64 Kbytes ROM Read Cycle
–
≤
64 Kbytes ROM Write Cycle
6.4.1 Target Timing
Tables 6.17 through 6.22 and Figures 6.11 through 6.16 describe
Target timing.