Avago Technologies LSI53C896 User Manual
Page 186
4-74
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
IRQM
IRQ Mode
3
When set, this bit enables a totem pole driver for the
INTA/, or INTB/ pin. When cleared, this bit enables an
open drain driver for the INTA/, or INTB/, pin with an
internal weak pull-up. The bit should remain cleared to
retain full PCI compliance.
STD
Start DMA Operation
2
The LSI53C896 SCSI function fetches a SCSI SCRIPTS
instruction from the address contained in the
register when this bit is
set. This bit is required if the LSI53C896 SCSI function is
in one of the following modes:
•
Manual start mode – Bit 0 in the
register is set
•
Single step mode – Bit 4 in the
register is set
When the LSI53C896 SCSI function is executing
SCRIPTS in manual start mode, the Start DMA bit must
be set to start instruction fetches, but need not be set
again until an interrupt occurs. When the LSI53C896 SCSI
function is in single step mode, set the Start DMA bit to
restart execution of SCRIPTS after a single step interrupt.
IRQD
INTA, INTB Disable
1
Setting this bit disables the INTA (for SCSI Function A),
or INTB (for SCSI Function B) pin. Clearing the bit
enables normal operation. As with any other register
other than
Interrupt Status Zero (ISTAT0)
,
this register cannot be accessed
except by a SCRIPTS instruction during SCRIPTS
execution. For details on the use of this bit in interrupt
handling, refer to
Chapter 2, “Functional Description.”
COM
LSI53C700 Family Compatibility
0
When the COM bit is cleared, the LSI53C896 SCSI
function behaves in a manner compatible with the
LSI53C700 family; selection/reselection IDs are stored in
both the
and
SCSI First Byte Received (SFBR)
registers. This bit is not
affected by a software reset.