3 i/o instructions, 1 first dword, I/o instructions – Avago Technologies LSI53C896 User Manual
Page 243: First dword, First 32-bit word of the i/o instruction, Section 5.3, “i/o instructions
I/O Instructions
5-15
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
5.3 I/O Instructions
This section contains information about the I/O Instruction register. It is
divided into
and
.
5.3.1 First Dword
Figure 5.5
First 32-Bit Word of the I/O Instruction
IT[1:0]
Instruction Type – I/O Instruction
[31:30]
OPC[2:0]
Opcode
[29:27]
The following Opcode bits have different meanings,
depending on whether the LSI53C896 is operating in the
initiator or target mode. Opcode selections 0b101–0b111
are considered Read/Write instructions, and are
described
Section 5.4, “Read/Write Instructions.”
Target Mode
Reselect Instruction
The LSI53C896 arbitrates for the SCSI bus by asserting
the SCSI ID stored in the
register.
If it loses arbitration, it tries again during the next
available arbitration cycle without reporting any lost
arbitration status.
If the LSI53C896 wins arbitration, it attempts to reselect
the SCSI device whose ID is defined in the destination ID
field of the instruction. When the LSI53C896 wins
31 30 29
27 26 25 24 23
20 19
16 15
11 10
9
8
7
6
5
4
3
2
0
DCMD Register
DBC Register
IT[1:0] OPC[2:0] RA TI Sel
R
ENDID[3:0]
R
CA TM
R
A
R
ATN
R
OPC2 OPC1 OPC0
Instruction Defined
0
0
0
Reselect
0
0
1
Disconnect
0
1
0
Wait Select
0
1
1
Set
1
0
0
Clear