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Avago Technologies LSI53C896 User Manual

Page 241

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Block Move Instructions

5-13

Version 3.3

Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.

SCSIP[2:0]

SCSI Phase

[26:24]

This 3-bit field defines the desired SCSI information
transfer phase. When the LSI53C896 operates in the
initiator mode, these bits are compared with the latched
SCSI phase bits in the

SCSI Status One (SSTAT1)

register. When the LSI53C896 operates in the target
mode, it asserts the phase defined in this field. The
following table describes the possible combinations and
the corresponding SCSI phase.

TC[23:0]

Transfer Counter

[23:0]

This 24-bit field specifies the number of data bytes to be
moved between the LSI53C896 and system memory. The
field is stored in the

DMA Byte Counter (DBC)

register.

When the LSI53C896 transfers data to/from memory, the
DBC register is decremented by the number of bytes
transferred. In addition, the

DMA Next Address (DNAD)

register is incremented by the number of bytes
transferred. This process is repeated until the DBC
register is decremented to zero. At this time, the
LSI53C896 fetches the next instruction.

If bit 28 is set, indicating table indirect addressing, this field
is not used. The byte count is instead fetched from a table
pointed to by the

Data Structure Address (DSA)

register.

MSG C_D

I_O

SCSI Phase

0

0

0

Data-Out

0

0

1

Data-In

0

1

0

Command

0

1

1

Status

1

0

0

Reserved-Out

1

0

1

Reserved-In

1

1

0

Message-Out

1

1

1

Message-In