Avago Technologies LSI53C896 - Manual (Page 169)

SCSI Registers 4-57
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
CM Configured as Memory 4
This bit is defined as the configuration memory enable
status bit. This read only bit indicates whether the chip is
currently enabled as memory space.
Note: Bits 4 and 5 may be set if the chip is mapped in both I/O
and memory space. Also, bits 4 and 5 may be set if the
chip is dual-mapped.
PCICIE PCI Configuration Info Enable 3
This bit controls the shadowing of the PCI
Base Address Register Two (SCRIPTS RAM) ,
PCI Base Address Register One (MEMORY), PCI
Device ID , and PCI Revision ID (Rev ID) into the
Scratch Register A (SCRATCHA) ,
Memory Move Read Selector (MMRS) ,
Scratch Register B (SCRATCHB) ,
Memory Move Write Selector (MMWS) , and
SCRIPTS Fetch Selector (SFS) registers.
When it is set, MMWS contains bits [63:32] and
SCRATCH B contains bits [31:0] of the RAM Base
Address value from the PCI Configuration
Base Address Register Two (SCRIPTS RAM) .
This is the base address for the internal 8 Kbytes internal
RAM.
Memory Move Read Selector (MMRS) contains bits
[63:32] and Scratch Register A (SCRATCHA) contains
bits [31:0] of the memory mapped operating register base
address. Bits [23:16] of
SCRIPTS Fetch Selector (SFS)
contain the PCI Revision ID (Rev ID) register value and
bits [15:0] contain the PCI Device ID register value. When
this bit is set, only reads to the registers are affected,
writes pass through normally.
When this bit is cleared, the SCRATCH A, MMRS,
SCRATCH B, MMWS, and SFS registers return to
normal operation.
Note: Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a Read-Modify-Write to
this register.