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5 designing an ultra2 scsi system, Designing an ultra2 scsi system – Avago Technologies LSI53C896 User Manual

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SCSI Functional Description

2-23

Version 3.3

Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.

2.2.5 Designing an Ultra2 SCSI System

Because Ultra2 SCSI is based on existing SCSI standards, it can use
existing driver programs as long as the software is able to negotiate for
Ultra2 SCSI synchronous transfer rates. Additional software
modifications may be needed to take advantage of the new features in
the LSI53C896.

In the area of hardware, LVD SCSI is required to achieve Ultra2 SCSI
transfer rates and to support the longer cable and additional devices on the
bus. All devices on the bus must have LVD SCSI capabilities to guarantee
Ultra2 SCSI transfer rates. For details on Ultra2 SCSI, refer to the SPI-2
working document which is available from the SCSI BBS referenced at the
beginning of this manual.

Chapter 6, “Specifications,”

contains Ultra2 SCSI

timing information. In addition to the guidelines in the draft standard, make
the following software and hardware adjustments to accommodate Ultra2
SCSI transfers:

Set the Ultra Enable bit to enable Ultra2 SCSI transfers.

Set the TolerANT Enable bit, bit 7 in the

SCSI Test Three (STEST3)

register, whenever the Ultra Enable bit is set.

Do not extend the SREQ/SACK filtering period with the

SCSI Test Two (STEST2)

register bit 1. When the Ultra Enable bit is

set, the filtering period is fixed at 8 ns for Ultra2 SCSI or 15 ns for
Ultra SCSI, regardless of the value of the SREQ/SACK filtering bit.

Use the SCSI clock quadrupler.

Using the SCSI Clock Quadrupler – The LSI53C896 can quadruple
the frequency of a 40 MHz SCSI clock, allowing the system to perform
Ultra2 SCSI transfers. This option is user selectable with bit settings in
the

SCSI Test One (STEST1)

,

SCSI Test Three (STEST3)

, and

SCSI Control Three (SCNTL3)

registers. At power-on or reset, the

quadrupler is disabled and powered down. Follow these steps to use the
clock quadrupler:

1.

Set the SCLK Quadrupler Enable bit (

SCSI Test One (STEST1)

register, bit 3).

2.

Poll bit 5 of the

SCSI Test Four (STEST4)

register. The LSI53C896

sets this bit as soon as it locks in the 160 MHz frequency. The
frequency lockin takes approximately 100 microseconds.