Avago Technologies LSI53C896 - Manual (Page 109)

Power and Ground Signals 3-21
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
3.6 Power and Ground Signals
Table 3.17 describes the signals for the Power and Ground Signals group.
Table 3.17 Power and Ground Signals
Name
1
Bump Type Strength Description
V
SS
D4, D12, D20, M4,
M10–14, M20, AA3,
AA21, K10–14, L10–14,
C3, C21, N10–14,
P10–14, Y4, Y12, Y20. G N/A Ground for PCI bus drivers/receivers, SCSI
bus drivers/receivers, local memory
interface drivers, and other I/O pins.
V
DD
D7, D10, D14, D17, G4,
G20, K4, K20, P4, P20,
U4, U20, Y7, Y10, Y14,
Y17. P N/A Power for PCI bus drivers/receivers, SCSI
bus drivers/receivers, local memory interface
drivers/receivers, and other I/O pins.
V
DD
-Core D3, E4, Y13, AB18. P N/A Power for core logic.
V
SS
-Core D2, F3, Y15, AB19,
AC21. G N/A Ground for core logic.
V
DD
-A C20 P N/A Power for analog cells (clock quadrupler
and diffsense logic).
V
SS
-A B20 G N/A Ground for analog cells (clock quadrupler
and diffsense logic).
V
DD
-Bias M22 P N/A Power for LVD bias current.
V
DD
-Bias2 A11 P N/A Power for LVD bias current.
RBIAS M21 I N/A Connects an external resistor to generate
the bias current used by LVDlink pads.
Resistor value should be 9.76 k
Ω
. Connect
other end of resistor to V
DD
.
NC A1, A2, A22, A23, B1–3,
B21–23, C2, C22, D21,
AB2, AB3, AC1, AC2,
AA22, AB22, AB23. N/A N/A These pins have no internal connection.
1. The I/O driver pad rows and digital core have isolated power supplies as indicated by the “I/O” and
“CORE” extensions on their respective V
SS
and V
DD
names. These power and ground pins should
be connected directly to the primary power and ground planes of the circuit board. Bypass capacitors
of 0.01
µ
F should be applied between adjacent V
SS
and V
DD
pairs wherever possible. Do not connect
bypass capacitors between V
SS
and V
DD
pairs that cross power and ground bus boundaries.