Avago Technologies LSI53C896 - Manual (Page 79)

SCSI Functional Description 2-51
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 2.8 Interrupt Routing Hardware Using the LSI53C896
Only one entity can control a mainboard SCSI core, or conflicts occur.
Typically, a SCSI core is controlled by the SCSI BIOS and an operating
system driver. When a SCSI core is allocated to a RAID adapter,
however, a mechanism must be implemented to prevent the SCSI BIOS
and operating system driver from trying to access the SCSI core. The
mainboard designer has several options to choose from for doing this.
The first option is to have the SCSI core load its PCI Subsystem ID using
a serial EPROM on power-up. If bit 15 in this ID is set, the LSI Logic
BIOS and operating system drivers ignore the chip. This makes it
possible to control the assignment of the mainboard SCSI cores using a
configuration utility.
The second option is to provide mainboard and system BIOS support for
NVS. The SCSI core may then be enabled or disabled using the SCSI
BIOS configuration utility. Not all versions of the LSI Logic drivers support
this capability.
The third option is to have the system BIOS not report the existence of
the SCSI controller chips when the SCSI BIOS and operating systems
make PCI BIOS calls. This approach requires modifications to the
system BIOS and assumes the operating system uses PCI BIOS calls
when searching for PCI devices.
A4
A6
A7
B8
B7
SCSI Core
I
SCSI Core
II
LSI53C896
ALT_INTA/
2.7 K
+ 5 V
INTA/
ALT_INTB/
INTB/
2.7 K
+ 5 V
INTB/
INTD/
INTA/
INTC/
TDI
+ 5 V
INT_DIR
PCI RAID
Upgrade
Slot INTA/
PCI RAID
Upgrade
Slot INTB/
Mbyte SCSI INTA/
Mbyte SCSI INTB/
These interrupt lines are
PCI slot interrupt lines as
determined by the mainboard
10 K PCI RAID Upgrade Slot
interrupt routing scheme.
connected to the other