2 second dword, Second dword, Second 32-bit word of the i/o instruction – Avago Technologies LSI53C896 User Manual
Page 250
5-22
SCSI SCRIPTS Instruction Set
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
R
Reserved
[8:7]
A
Set/Clear SACK/
6
R
Reserved
[5:4]
ATN
Set/Clear SATN/
3
These two bits are used in conjunction with a Set or
Clear instruction to assert or deassert the corresponding
SCSI control signal. Bit 6 controls the SCSI SACK/
signal. Bit 3 controls the SCSI SATN/ signal.
The Set instruction asserts SACK/ and/or SATN/ on the
SCSI bus. The Clear instruction deasserts SACK/ and/or
SATN/ on the SCSI bus. The corresponding bit in the
SCSI Output Control Latch (SOCL)
register is set or
cleared depending on the instruction used.
Because SACK/ and SATN/ are initiator signals, they are
not asserted on the SCSI bus unless the LSI53C896 is
operating as an initiator or the SCSI Loopback Enable bit
is set in the
register.
The Set/Clear SCSI ACK/, ATN/ instruction is used after
message phase Block Move operations to give the initiator
the opportunity to assert attention before acknowledging
the last message byte. For example, if the initiator wishes
to reject a message, it issues an Assert SCSI ATN
instruction before a Clear SCSI ACK instruction.
R
Reserved
[2:0]
5.3.2 Second Dword
Figure 5.6
Second 32-Bit Word of the I/O Instruction
SA
Start Address
[31:0]
This 32-bit field contains the memory address to fetch the
next instruction if the selection or reselection fails.
If relative or table relative addressing is used, this value
is a 24-bit signed offset relative to the current
register value.
31
0
DSPS Register