Avago Technologies LSI53C896 - Manual (Page 39)

PCI Functional Description 2-11
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.1.3 Internal Arbiter
The PCI to SCSI controller uses a single REQ/ - GNT/ signal pair to
arbitrate for access to the PCI bus. An internal arbiter circuit allows the
different bus mastering functions resident in the chip to arbitrate among
themselves for the privilege of arbitrating for PCI bus access. There are
two independent bus mastering functions inside the LSI53C896, one for
each of the SCSI functions.
The internal arbiter uses a round robin arbitration scheme to decide
which internal bus mastering function may arbitrate for access to the PCI
bus. This ensures that no function is starved for access to the PCI bus.
2.1.4 PCI Cache Mode
The LSI53C896 supports the PCI specification for an 8-bit Cache Line Size
register located in the PCI configuration space. The Cache Line Size
register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the
Cache Line Size register, the PCI commands Memory Read Line,
Memory Read Multiple, Memory Write and Invalidate are each
software enabled or disabled to allow the user full flexibility in using
these commands.
2.1.4.1 Enabling Cache Mode
For the cache logic to be enabled to issue PCI cache commands
(Memory Read Line, Memory Read Multiple, and Memory Write and
Invalidate) on any given PCI master operation the following conditions
must be met:
•
The Cache Line Size Enable bit in the DMA Control (DCNTL) register
must be set.
•
The PCI Cache Line Size register must contain a valid binary cache
size, that is, 2, 4, 8, 16, 32, 64, or 128 Dwords. Only these values
are considered valid cache sizes.
•
The programmed burst size (in Dwords) must be equal to or greater
than the cache line size register. The
DMA Mode (DMODE) register
bits [7:6] and the Chip Test Five (CTEST5) register bit 2 are the burst
length bits.