Avago Technologies LSI53C896 - Manual (Page 83)

Parallel ROM Interface 2-55
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
and the transfer takes place normally. For “N” consecutive wide data
receive Block Move instructions, the 2nd through the Nth Block Move
instructions should be chained block moves.
For send data (Data-Out for the initiator or Data-In for the target), a
chained Block Move instruction indicates that if a partial transfer
terminates, the chained block move instruction, the last low-order byte
(the partial memory transfer) should be stored in the lower byte of the
SCSI Output Data Latch (SODL) register and not sent across the SCSI
bus. Without the chained Block Move instruction, the last low-order byte
would be sent across the SCSI bus. The starting byte count represents
data bytes transferred from memory but not to the SCSI bus when a
partial transfer exists. For example, if the instruction is an Initiator
chained Block Move Data Out of five bytes (and WSS is not previously
set), five bytes are transferred out of memory to the SCSI controller, four
bytes are transferred from the SCSI controller across the SCSI bus, and
one byte is temporarily stored in the lower byte of the SODL register
waiting to be married with the first byte of the next Block Move
instruction. Regardless of whether a chained Block Move or normal
Block Move instruction is used, if the WSS bit is set at the start of a data
send command, the first byte of the data send command is assumed to
be the high-order byte and is “married” with the low-order byte stored in
the lower byte of the SODL register before the two bytes are sent across
the SCSI bus. For “N” consecutive wide data send Block Move
commands, the first through the (N
th −
1) Block Move instructions should
be Chained Block Moves.
2.3 Parallel ROM Interface
The LSI53C896 supports up to one megabyte of external memory in
binary increments from 16 Kbytes to allow the use of expansion ROM for
add-in PCI cards. Both functions of the device share the ROM interface.
This interface is designed for low speed operations such as downloading
instruction code from ROM. It is not intended for dynamic activities such
as executing instructions.
System requirements include the LSI53C896, two or three external 8-bit
address holding registers (HCT273 or HCT374), and the appropriate
memory device. The 4.7 k
Ω
pull-up resistors on the MAD bus require HC
or HCT external components. If in-system Flash ROM updates are