Chip test six (ctest6), Register: 0x23 – Avago Technologies LSI53C896 User Manual
Page 176
4-64
Registers
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
the DMAWR signal indicates that data is transferred from
the SCSI bus to the host bus. Deasserting the DMAWR
signal transfers data from the host bus to the SCSI bus.
BL2
Burst Length Bit 2
2
This bit works with bits 6 and 7 (BL[1:0]) in the
,
register to determine the
burst length. For complete definitions of this field, refer to
the descriptions of DMODE bits 6 and 7. This bit is
disabled if an 112-byte FIFO is selected by clearing the
DMA FIFO Size bit.
BO[9:8]
DMA FIFO Byte Offset Counter, Bits [9:8]
[1:0]
These are the upper two bits of the DFBOC. The DFBOC
consists of these bits and the
bits [7:0].
Register: 0x23
Chip Test Six (CTEST6)
Read/Write
DF[7:0]
DMA FIFO
[7:0]
Writing to this register writes data to the appropriate byte
lane of the DMA FIFO as determined by the FBL bits in
the
register. Reading this
register unloads data from the appropriate byte lane of
the DMA FIFO as determined by the FBL bits in the
CTEST4 register. Data written to the FIFO is loaded into
the top of the FIFO. Data read out of the FIFO is taken
from the bottom. To prevent DMA data from being
corrupted, this register should not be accessed before
starting or restarting SCRIPTS operation. Write to this
register only when testing the DMA FIFO using the
register. Writing to this register
while the test mode is not enabled produces
unexpected results.
7
0
DF[7:0]
0
0
0
0
0
0
0
0