Avago Technologies LSI53C896 - Manual (Page 323)

PCI and External Memory Interface Timing Diagrams 6-55
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.31 Slow Memory (
≥
128 Kbytes) Read Cycle
Figure 6.31 Slow Memory (
≥
128 Kbytes) Read Cycle (Cont.)
CLK
(Driven by System)
1 2 3 4 5 6 7 8 9 10
MAD
(Addr driven by LSI53C896
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C896)
MAS0/
(Driven by LSI53C896)
MCE/
(Driven by LSI53C896)
MOE/
(Driven by LSI53C896)
MWE/
(Driven by LSI53C896)
t
13
t
11 t
12
t
15
t
16
Data drvn by mem)
t
14
CLK
(Driven by System)
Data Driven by Memory)
11 12 13 14 15 16 17 18 19 20
MAD
(Addr driven by LSI53C896;
MAS1/
(Driven by LSI53C896)
MAS0/
(Driven by LSI53C896)
MCE/
(Driven by LSI53C896)
MOE/
(Driven by LSI53C896)
MWE/
(Driven by LSI53C896)
t
15
21
Read
Data
t
19
t
17
t
14
t
16
Valid
t
18
22