Avago Technologies LSI53C896 - Manual (Page 108)

3-20 Signal Descriptions
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
3.5 Test Interface Signals
This section describes the signals for the Test Interface group. Table 3.16
is divided into Internal Test Signals and JTAG Signals .
Table 3.16 Test Interface Signals
Name Bump Type Strength Description
Internal Test Signals
TEST_HSC C23 I N/A Test Halt SCSI Clock. For LSI Logic test purposes
only. Pulled LOW internally. This signal can also cause
a full chip reset.
TEST_RST/ C1 I N/A Test Reset. For LSI Logic test purposes only. Pulled
HIGH internally.
MOE/_
TESTOUT Y18 O 4 mA Memory Output Enable. This pin is used as an
output enable signal to an external EPROM or flash
memory during read operations. It also tests the
connectivity of the LSI53C896 signals in the
“AND-tree” test mode. The MOE/_TESTOUT pin is
only driven as the test out function when the ZMODE
bit (
Chip Control 1 (CCNTL1) , bit 7) is set.
JTAG Signals
TCK D1 I N/A Test Clock. This pin provides the clock for the JTAG
test logic.
TMS E3 I N/A Test Mode Select. The signal received at TMS is
decoded by the TAP controller to control JTAG test
operations.
TDI E2 I N/A Test Data In. Serial test instructions are received by
the JTAG test logic at this pin.
TDO E1 O 4 mA Test Data Out. This pin is the serial output for test
instructions and data from the JTAG test logic.
Reserved AB14 N/A N/A Reserved. Not Used.